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april 2005 copyright ? alliance semiconduc tor. all rights reserved. ? AS7C33512NTD32A as7c33512ntd36a 4/21/05, v 2.8 alliance semiconductor p. 1 of 18 3.3v 512k 32/36 pipeli ned sram with ntd tm features ? organization: 524,288 words 32 or 36 bits ?ntd ? architecture for effi cient bus operation ? fast clock speeds to 166 mhz ? fast clock to data access: 3.4/3.8 ns ?fast oe access time: 3.4/3.8 ns ? fully synchronous operation ? asynchronous output enable control ? available in 100-pin tqfp packages ? individual byte write and global write ? clock enable for operation hold ? multiple chip enables for easy expansion ? 3.3v core power supply ? 2.5v or 3.3v i/o operation with separate v ddq ? self-timed write cycles ? interleaved or linear burst modes ? snooze mode for standby operation logic block diagram selection guide -166 -133 units minimum cycle time 6 7.5 ns maximum clock frequency 166 133 mhz maximum clock access time 3.4 3.8 ns maximum operating current 300 275 ma maximum standby current 90 80 ma maximum cmos standby current (dc) 60 60 ma write buffer address d q clk register output register dq[a,b,c,d] 19 19 clk ce0 ce1 ce2 a[18:0] oe clk cen control clk logic data d q clk input register 32/36 32/36 oe 512k x 32/36 sram array r/w dq[a,b,c,d] bwb bwd clk q d adv / ld lbo burst logic addr. registers write delay 19 zz clk 32/36 32/36 32/36 32/36 bwc bwa
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 2 of 18 16 mb synchronous sram products list 1,2 1 core power supply: vdd = 3.3v + 0.165v 2 i/o supply voltage: vddq = 3.3v + 0.165v for 3.3v i/o vddq = 2.5v + 0.125v for 2.5v i/o 3 refer corresponding product datasheets fo r the latest information on clock speed and clock access time availability. pl-scd : pipelined burst synchronous sram - single cycle deselect pl-dcd : pipelined burst synchronous sram - double cycle deselect ft : flow-through burst synchronous sram ntd 1 -pl : pipelined burst synchronous sram with ntd tm ntd-ft : flow-through burst s ynchronous sram with ntd tm org part number mode speed 3 1mx18 as7c331mpfs18a pl-scd 166/133 mhz 512kx32 as7c33512pfs32a pl-scd 166/133 mhz 512kx36 as7c33512pfs36a pl-scd 166/133 mhz 1mx18 as7c331mpfd18a pl-dcd 166/133 mhz 512kx32 as7c33512pfd32a pl-dcd 166/133 mhz 512kx36 as7c33512pfd36a pl-dcd 166/133 mhz 1mx18 as7c331mft18a ft 7.5/8.5/10 ns 512kx32 as7c33512ft32a ft 7.5/8.5/10 ns 512kx36 as7c33512ft36a ft 7.5/8.5/10 ns 1mx18 as7c331mntd18a ntd-pl 166/133 mhz 512kx32 AS7C33512NTD32A ntd-pl 166/133 mhz 512kx36 as7c33512ntd36a ntd-pl 166/133 mhz 1mx18 as7c331mntf18a ntd-ft 7.5/8.5/10 ns 512kx32 as7c33512ntf32a ntd-ft 7.5/8.5/10 ns 512kx36 as7c33512ntf36a ntd-ft 7.5/8.5/10 ns 1. ntd: no turnaround delay. ntd tm is a trademark of alliance semiconducto r corporation. all trademarks mentione d in this document are the property of their respective owners.
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 3 of 18 100-pin tqfp - top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lbo a a a a a1 a0 nc nc v ss v dd nc nc a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 bwd bwc bwb bwa ce2 v dd v ss clk r/w cen oe adv/ld a a a a tqfp 14 x 20mm a nc/dqpc dqc0 dqc1 v ddq v ssq dqc2 dqc3 dqc4 dqc5 v ssq v ddq dqc6 dqc7 nc v dd nc v ss dqd0 dqd1 v ddq v ssq dqd2 dqd3 dqd4 dqd5 v ssq v ddq dqd6 dqd7 nc/dqpd dqpb/nc dqb7 dqb6 v ddq v ssq dqb5 dqb4 dqb3 dqb2 v ssq v ddq dqb1 dqb0 v ss zz dqa7 dqa6 v ddq v ssq dqa5 dqa4 dqa3 dqa2 v ssq v ddq dqa1 dqa0 dqpa/nc v dd nc note: for pins 1, 30, 51, and 80, nc applies to the x32 configuration. dqpn applies to the x36 configuration.
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 4 of 18 functional description the AS7C33512NTD32A/36a family is a high performance cmos 16 mbit synchronous static random access memory (sram) organized as 524,288 words 32 or 36 bits and incorporates a late late write. this variation of the 16mb+ synchronous sram uses the no turnaround delay (ntd ? ) architecture, feat uring an enhanced write operation that improves bandwidth over pipelined burs t devices. in a normal pipelined burst device, the write data, command, and address are all ap plied to the device on the same clock edge. if a read command foll ows this write command, the system must wait for two 'dead' cycles for valid data to become available. th ese dead cycles can significantly reduce overall bandwidth for applicati ons requiring random access or read-modify -write operations. ntd ? devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-through read latency. wr ite data is applied two cycles after the write command and addr ess, allowing the read pipeline to clear. with ntd ? , write and read operations can be used in any order without producing dead bus cycles. assert r/w low to perform write cycles. byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes. write enable signals, along with the write address, are registered on a rising ed ge of the clock. write data is applied to the device two clock cycles later. unlike some asynchronous srams, output enable oe does not need to be toggled for write operations; it can be tied low for normal operations. outputs go to a high impedance state when the device is de- selected by any of the three chip enable inputs. in pipelined m ode, a two cycle deselect latency allows pending read or write operations to be completed. use the adv (burst advance) input to perform burst read, write and deselect operations. when adv is high, external addresses, c hip select, r/w pins are ignored, and internal address counters increment in the count sequence specified by the lbo control. any device operations, including burst, can be stalled using the cen =1, the clock enable input. the AS7C33512NTD32A/36a operates with a 3.3v 5% power supply for the device core (v dd ). dq circuits use a separate power supply (v ddq ) that operates across 3.3v or 2.5v ranges. these devices are available in a 100-pin tqfp package. tqfp capacitance * guaranteed not tested tqfp thermal resistance parameter symbol test conditions min max unit input capacitance c in * v in = 0v - 5 pf i/o capacitance c i/o * v out = 0v - 7 pf description conditions symbol typical units thermal resistance (junction to ambient) 1 1 this parameter is sampled test conditions follow st andard test methods and procedures for measuring thermal impedance, pe r eia/jesd51 1?layer ja 40 c/w 4?layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8 c/w
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 5 of 18 signal descriptions snooze mode snooze mode is a low current , power-down mode in which the device is deselected and current is reduced to i sb2 . the duration of snooze mode is dictated by the lengt h of time the zz is in a high state. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. after entering snooz e mode, all inputs except zz is disabled and all outputs go to high-z. any operation pending when entering snooze mode is not guaranteed to successfully com plete. therefore, snooze mode (read or write) must not be initiated until valid pending operations are completed. similarly, when exit ing snooze mode during t pus , only a deselect or read cycle should be given wh ile the sram is transitioning out of snooze mode. signal i/o properties description clk i clock clock. all inputs except oe , lbo , and zz are synchronous to this clock. cen i sync clock enable. when de-asserted high, the clock input signal is masked. a, a0, a1 i sync address. sampled when all chip enables are active and adv/ld is asserted. dq[a,b,c,d] i/o sync data. driven as outp ut when the chip is enabled and oe is active. ce0 , ce1, ce2 i sync synchronous chip enables. sampled at the rising edge of clk, when adv/ld is asserted. are ignored when adv/ld is high. adv/ld i sync advance or load. when sampled high, the internal burst address counter will increment in the order defined by the lbo input value. when low, a new address is loaded. r/w i sync a high during load initiates a read operation. a low during load initiates a write operation. is ignored when adv/ld is high. bw[a,b,c,d] i sync byte write enables. used to control write on individual bytes. sampled along with write command and burst write. oe i async asynchronous output enable. i/o pins are not driven when oe is inactive. lbo istatic selects burst mode. when tied to v dd or left floating, device follows interleaved burst order. when driven low, device follows linear burst order. this signal is internally pulled high. zz i async snooze. places device in low power mode; data is retained. connect to gnd if unused. this signal is inte rnally pulled low. nc - - no connect
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 6 of 18 burst order synchronous truth table [5,6,7,8,9,11] key : x = don?t care, h = high, l = low. bw n = h means all byte write signals (bw a, bw b, bw c, and bw d) are high. bw n = l means one or more byte write signals are low. notes: 1 continue burst cycles, whether read or writ e, use the same control inputs. the type of cycle performed (rea d or write) is cho se in the initial begin burst cycle. a coninue deselect cycle can only be entered if a deselect cycle is executed first. 2 dummy read and write abort cycles can be considered nops because the device performs no external operation. a write abort mea ns a write command is given, but no operation is performed. 3 oe may be wired low to minimize the number of control signal to the sram. the device will automati cally turn off the output drive rs during a write cycle. oe may be used when the bus turn-on and turn-off times do not meet an application?s requirements. 4 if an inhibit clock command occurs during a read operation, the dq bus will remain active (low-z). if it occurs during a wri te cycle, the bus will remain in high-z. no write operations will be performed during th e inhibit clock cycle. 5 bw a enables writes to byte ?a? (dqa pins); bw b enables writes to byte ?b? (dqb pins); bw c enables writes to byte ?c? (dqc pins); bw d enables writes to byte ?d? (dqd pins). 6 all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 7 wait states are inserted by setting cen high. 8 this device contains circuitry that will ensure that the outputs will be in high-z during power-up. 9 the device incorporates a 2-bit burs t counter. address wraps to the initial address ev ery fourth burst cycle. 10 the address counter is incremented for all continue burst cycles. 11 zz pin is always low in this truth table. interleaved burst order (lbo = 1) linear burst order (lbo = 0) a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 starting address 0 0 0 1 1 0 1 1 starting address 0 0 0 1 1 0 1 1 first increment 0 1 0 0 1 1 1 0 f irst increment 0 1 1 0 1 1 0 0 second increment 1 0 1 1 0 0 0 1 s econd increment 1 0 1 1 0 0 0 1 third increment 1 1 1 0 0 1 0 0 third increment 1 1 0 0 0 1 1 0 ce0 ce1 ce2 adv/ld r/w bw n oe cen address source clk operation dq notes h x x l x x x l na l to h deselect cycle high-z x x h l x x x l na l to h deselect cycle high-z x l x l x x x l na l to h deselect cycle high-z x x x h x x x l na l to h continue deselect cycle high-z 1 l h l l h x l l external l to h read cycle (begin burst) q x x x h x x l l next l to h read cycle (continue burst) q 1,10 l h l l h x h l external l to h nop/dummy read (begin burst) high-z 2 x x x h x x h l next l to h dummy read (continue burst) high-z 1,2,10 l h l l l l x l external l to h write cycle (begin burst) d 3 x x x h x l x l next l to h write cycle (continue burst) d 1,3,10 l h l l l h x l external l to h nop/write abort (begin burst) high-z 2,3 x x x h x h x l next l to h write abort (continue burst) high-z 1,2,3, 10 x x x x x x x h current l to h inhibit clock - 4
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 7 of 18 state diagram for ntd sram absolute maximum ratings stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions ou tside those indicated in the opera tional sections of this specificat ion is not implied. exposure to absolute maximum rating conditions may affect reliability. recommended operating conditions at 3.3v i/o * v ddq cannot be greater than v dd recommended operating conditions at 2.5v i/o * v ddq cannot be greater than v dd parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.5 +4.6 v input voltage relative to gnd (input pins) v in ?0.5 v dd + 0.5 v input voltage relati ve to gnd (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w short circuit output current i out ? 20 ma storage temperature t stg ?65 +150 o c temperature under bias t bias ?65 +135 o c parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq * 3.135 3.3 v dd v ground supply vss 0 0 0 v parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq * 2.375 2.5 v dd v ground supply vss 0 0 0 v dsel dsel r ea d read burst burst read writ burs read write d s e l r e a d burst write dsel d s e l w r i t e w r i t e burst dsel burst burst write read
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 8 of 18 dc electrical characteristics for 3.3v i/o operation dc electrical characteristics for 2.5v i/o operation ? lbo and zz pins have an internal pull-up or pull-down, and input leakage = 10 a. * v ih max < vdd +1.5v for pulse width less than 0.2 x t cyc ** v il min = -1.5 for pulse width less than 0.2 x t cyc i dd operating conditions and maximum limits parameter sym conditions min max unit input leakage current ? |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 2* v dd +0.3 v i/o pins 2* v ddq +0.3 input low (logic 0) voltage v il address and control pins -0.3** 0.8 v i/o pins -0.5** 0.8 output high voltage v oh i oh = ?4 ma, v ddq = 3.135v 2.4 ? v output low voltage v ol i ol = 8 ma, v ddq = 3.465v ? 0.4 v parameter sym conditions min max unit input leakage current ? |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 1.7* v dd +0.3 v i/o pins 1.7* v ddq +0.3 v input low (logic 0) voltage v il address and control pins -0.3** 0.7 v i/o pins -0.3** 0.7 v output high voltage v oh i oh = ?4 ma, v ddq = 2.375v 1.7 ? v i oh = ?1 ma, v ddq = 2.375v 2.0 ? output low voltage v ol i ol = 8 ma, v ddq = 2.625v ? 0.7 v i ol = 1 ma, v ddq = 2.625v ? 0.4 parameter sym conditions -166 -133 unit operating power supply current 1 1 i cc given with no output loading. i cc increases with faster cycle times and greater output loading. i cc ce0 < v il , ce1 > v ih , ce2 < v il , f = f max , i out = 0 ma, zz < v il 300 275 ma standby power supply current i sb all v in 0.2v or > v dd ? 0.2v, deselected, f = f max , zz < v il 90 80 ma i sb1 deselected, f = 0, zz < 0.2v, all v in 0.2v or v dd ? 0.2v 60 60 i sb2 deselected, f = f max , zz v dd ? 0.2v, all v in v il or v ih 50 50
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 9 of 18 timing characteristics over operating range snooze mode electrical characteristics parameter sym -166 -133 unit notes 1 1 see ?notes? on page 15. min max min max clock frequency f max ? 166 ? 133 mhz cycle time t cyc 6?7.5? ns clock access time t cd ?3.4?3.8 ns output enable low to data valid t oe ?3.4?3.8 ns clock high to output low z t lzc 0 ? 0 ? ns 2,3,4 data output invalid from clock high t oh 1.5 ? 1.5 ? ns 2 output enable low to output low z t lzoe 0 ? 0 ? ns 2,3,4 output enable high to output high z t hzoe ?3.4?3.8 ns 2,3,4 clock high to output high z t hzc ?3.4?3.8 ns 2,3,4 clock high pulse width t ch 2.4 ? 2.4 ? ns 5 clock low pulse width t cl 2.3 ? 2.4 ? ns 5 address and control setup to clock high t as 1.5 ? 1.5 ? ns 6 data setup to clock high t ds 1.5 ? 1.5 ? ns 6 write setup to clock high t ws 1.5 ? 1.5 ? ns 6, 7 chip select setup to clock high t css 1.5 ? 1.5 ? ns 6, 8 address hold from clock high t ah 0.5 ? 0.5 ? ns 6 data hold from clock high t dh 0.5 ? 0.5 ? ns 6 write hold from clock high t wh 0.5 ? 0.5 ? ns 6, 7 chip select hold from clock high t csh 0.5 ? 0.5 ? ns 6, 8 clock enable setup to clock high t cens 1.5 ? 1.5 ? ns 6 clock enable hold from clock high t cenh 0.5 ? 0.5 ? ns 6 adv setup to clock high t advs 1.5 ? 1.5 ? ns 6 adv hold from clock high t advh 0.5 ? 0.5 ? ns 6 description conditions symbol min max units current during snooze mode zz > v ih i sb2 50 ma zz active to input ignored t pds 2cycle zz inactive to input sampled t pus 2cycle zz active to snooze current t zzi 2cycle zz inactive to exit snooze current t rzzi 0cycle
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 10 of 18 key to switching waveforms timing waveform of read cycle undefined falling input rising input don?t care t ch t cyc t cl t as clk cen r/w t ceh a1 a2 a3 address t ah t ces t ws t wh ce0 ,ce2 t advs t csh dout ce1 t advh t oe t lzoe t hzoe q(a1) q(a2y?01) q(a2) q(a3) t hlzc oe adv/ld bwn t ws t wh q(a2y?10) q(a2y?11) read q(a1) dsel read q(a2) continue read q (a2y?01) continue read q (a2y?10) continue read q (a2y?11) inhibit clock read q(a3) continue read q (a3y?01)
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 11 of 18 timing waveform of write cycle t ch t cyc t cl t as clk cen r/w t ceh a1 a2 a3 address t ah t ces ce0 ,ce2 t advs t csh din ce1 t advh t hzoe d(a1) d(a2) d(a3) t ds oe adv/ld t dh q(n-2) dout bwn q(n-1) d(a2y?01) d(a2y?10) d(a2y?11) write d(a1) dsel write d(a2) continue write d (a2y?01) continue write d (a2y?10) continue write d (a2y?11) inhibit clock write d(a3) continue write d (a3y?01)
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 12 of 18 timing waveform of read/write cycle note: y = xor when lbo = high/no connect. y = add when lbo = low. bw[a:d] is don?t care. t ch t cyc t cl t cens t oh t oe clk cen ce0 , ce2 adv/ld r/w address d/q oe command t hzoe bwn a2 a1 a3 a5 a4 a7 a6 d(a1) d(a5) q(a6) d(a2) d(a2 y 01) q(a3) q(a4) q(a4 y 01 ) t cenh t ds t dh t lzc t cd t hzc t lzoe read q(a3) read q(a4) burst read q(a4y01) write d(a5) read q(a6) write d(a7) dsel t css t advh t ws t wh t ws t wh ce1 write d(a1) write d(a2) t advs t csh t as t ah burst write d(a2y01)
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 13 of 18 nop, stall and deselect cycles note: y = xor when lbo = high/no connect; y = add when lbo = low. oe is low. clk cen ce0 , ce2 adv/ld r/w address d/q command bwn a1 a2 q(a1) d(a2) q(a1 y 01) q(a1 y 10) burst q(a1y01 ) stall dsel burst dsel write d(a2) burst nop d(a2y01 ) write nop d(a3) a3 read q(a1) burst q(a1y10 ) burst d(a2y10) ce1
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 14 of 18 timing waveform of snooze mode clk all inputs zz t zzi i supply (except zz) dout t pus zz recovery cycle i sb2 t rzzi zz setup cycle deselect or read only deselect or read only normal operation cycle high-z
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 15 of 18 ac test conditions notes 1) for test conditions, s ee ?ac test conditions?, figures a, b, and c 2) this parameter measured with output load condition in figure c. 3) this parameter is samp led, but not 100% tested. 4) t hzoe is less than t lzoe , and t hzc is less than t lzc at any given temperature and voltage. 5) t ch is measured high above v ih , and t cl is measured low below v il 6) this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk. all ot her synchronous inputs must meet the setup and hold tim es with stable logic levels for all ri sing edges of clk when chip is enabled. 7) write refers to r/ w and bw[a,b,c,d] . 8) chip select refers to ce0 , ce1, and ce2 . ? output load: for t lzc , t lzoe , t hzoe , and t hzc , see figure c. for all others, see figure b. ? input pulse level: gnd to 3v. see figure a. ? input rise and fall time (measured at 0.3v and 2.7v): 1.0v/ns. see figure a. ? input and output timing reference levels: 1.5v. d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v v l = 1.5v for 3.3v i/o; = v ddq /2 for 2.5v i/o thevenin equivalent: 353 ? /1538 ? 5 pf* 319 ? /1667 ? d out gnd figure c: output load(b) *including scope and jig capacitance +3.3v for 3.3v i/o; /+2.5v for 2.5v i/o
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 16 of 18 package dimensions 100-pin quad flat pack (tqfp) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b0.220.38 c0.090.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.85 16.15 he 21.80 22.20 l0.450.75 l1 1.00 nominal 0 7 dimensions in millimeters a1 a2 l1 l c he e hd d b e
? AS7C33512NTD32A/36a 4/21/05, v 2.8 alliance semiconductor p. 17 of 18 ordering information notes: add suffix ?n? to the above part number for lead free parts (ex. AS7C33512NTD32A-166tqcn) part numbering guide 1. alliance semicond uctor sram prefix 2. operating voltage: 33 = 3.3v 3. organization: 512 = 512k 4. ntd? = no turn-around delay, pipelined mode. 5. organization: 32 = x 32, 36 = x 36 6. production version: a = first production version 7. clock speed (mhz) 8. package type: tq = tqfp 9. operating temperature: c = commercial ( 0 c to 70 c); i = industrial ( -40 c to 85 c) 10. n = lead free part package & width ?166 ?133 tqfp x32 AS7C33512NTD32A-166tqc AS7C33512NTD32A-133tqc AS7C33512NTD32A-166tqi AS7C33512NTD32A-133tqi tqfp x36 as7c33512ntd36a-166tqc as7c33512ntd36a-133tqc as7c33512ntd36a-166tqi as7c33512ntd36a-133tqi as7c 33 512 ntd 32/36 a ?xxx tq c/i x 1 23 45678 910
? alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number:AS7C33512NTD32A/36a document version: v 2.8 ? copyright 2003 alliance semicondu ctor corporation. all rights re served. our three-point logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all othe r brand and product names may be the trademarks of their respec tive companies. alliance reserve s the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that ma y appear in this document. the data contained herein represents alliance's best da ta and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without noti ce. if the product described herein is under development, significant changes to the se specifications are possible. the information in this product data sheet is intended to be gene ral descriptive informati on for potential customers and users, and is not intended to operate as, or provid e, any guarantee or warrantee to any user or customer. alliance does not assume any responsibi lity or liability arising out of the application or use of any product described herein, and disclaims any express or imp lied warranties related to the s ale and/or use of alliance products including liability or wa rranties related to fitness for a particular pu rpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are ava ilable from alliance). all sales of allian ce products are made exclusively according to alliance's terms an d conditions of sale. the purchase of prod ucts from alliance does not convey a lice nse under any patent rights, copyrights; mask works rights, trad emarks, or any other intellect ual property rights of alliance or third parties. alli ance does not authorize its products for use as critical components in life-supporting system s where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the incl usion of alliance products in such life-supporti ng systems implies that the manufacturer assume s all risk of such use and agrees to indemnify alliance against all claims arising from such use. AS7C33512NTD32A/36a ?

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